Field of the Invention
The present invention relates to the design of circuit systems comprising logic gates, and more particularly, to such systems, even though they are subject to component failures leading to erroneous logic values occurring therein, that they have a design such that those faults which occur can be successfully found by testing.
Circuit systems for performing complicated logic functions based on both combinational and sequential logic circuits continue to find wider usage. This is the result of many factors, but primary among them are decreasing costs of, and decreasing amounts of space being taken by (increases in packing density) such systems. As a result, it is possible to make many improvements, some bordering on revolutionary, in many manufactured articles and to provide new kinds of items not previously available.
Increasing logic circuit density is primarily the result of increasing logic gate density in monolithic integrated circuits, although significant advances have also been made in miniaturizing the housings used for such integrated circuits. Such increases in logic gate density in monolithic integrated circuits have gotten to the point where tens of thousands of gates can be provided in a single monolithic circuit chip, and chips with hundreds of thousands of gates are at hand. Such large numbers of logic gates in a single chip can lead to very significant testing problems because faults which can occur in any of thousands of gates must be observable at a relatively few output terminations on the chip, terminations numbering not more than a few hundred at most. A circuit system which is not carefully designed can lead to logic gate arrangements having faults occur therein which are simply not observed at all at chip terminals, or can only be observed after an uneconomic amount of testing is conducted on such chips.
Therefore, a technique is desired which can evaluate proposed circuit system designs to determine the testability thereof. One method is the use of computer simulation. This is based on representing in a computer system a proposed design where the computer can then be directed to supply various input logic values for the circuit system inputs and determine the logic values which would result on each of the logic gate outputs and the circuit system outputs. Fault-free simulation of the logical operation of the circuit without faults can then be used to verify that the proposed circuit system design will yield the proper logic values at the circuit system outputs for the logic values selected to be applied to the circuit system inputs.
There is also the further possibility of simulating faulty circuit systems. Each logic gate input can sequentially be assumed to be stuck at a zero value or, alternatively, at a one value and the circuit performance thereafter simulated to determine the effect of such a fault. However, for circuit systems having a large number of logic gates, the cost of such a simulation becomes prohibitive. An alternative is to simulate the performance based on a random subset of possible faults which can occur in the proposed design. This arrangement does not provide much information concerning possible faults for which the resulting effects were not simulated.
A further possibility is to use a statistical fault analysis approach which needs only a fault-free simulation for evaluation. Such an analysis is based on estimating the probabilities of a logic gate input taking a particular logic value and having an effect at the circuit system output. Whether this effect occurs depends on the various other inputs to the logic gate taking on values during tests which permit the logic gate input of interest, taking on such a logic value, to have an effect on one or more of the circuit system outputs. Such an analysis can provide a substantial indication of the testability of a proposed circuit design.
Therefore, a statistical analysis which can be used with any kind of logic gate connected in any kind of interconnection configuration would be very desirable if it did not increase costs of the computer simulations to uneconomic levels. Such a capability would permit evaluating integrated circuit chip designs prior to fabricating test or prototype chips, a provision which becomes quite expensive where the incorporated design is found to be substantially unusable.